추가 적립 안내

Foreword vii
Paul Menchini
Preface xvii
Fundamental Concepts 1 (26)
Modeling Digital Systems 2 (2)
Domains and Levels of Modeling 4 (3)
Modeling Languages 7 (1)
VHDL Modeling Concepts 8 (8)
Elements of Behavior 9 (1)
Elements of Structure 10 (1)
Mixed Structural and Behavioral Models 10 (2)
Test Benches 12 (2)
Analysis, Elaboration and Execution 14 (2)
Learning a New Language: Lexical Elements 16 (11)
and Syntax
Lexical Elements 17 (5)
Syntax Descriptions 22 (3)
Exercises 25 (2)
Scalar Data Types and Operations 27 (26)
Constants and Variables 28 (2)
Constant and Variable Declarations 28 (1)
Variable Assignment 29 (1)
Scalar Types 30 (13)
Type Declarations 30 (1)
Integer Types 31 (2)
Floating-Point Types 33 (1)
Physical Types 34 (3)
Enumeration Types 37 (6)
Type Classification 43 (3)
Subtypes 44 (1)
Type Qualification 45 (1)
Type Conversion 45 (1)
Attributes of Scalar Types 46 (3)
Expressions and Operators 49 (4)
Exercises 51 (2)
Sequential Statements 53 (28)
If Statements 54 (3)
Case Statements 57 (5)
Null Statements 62 (1)
Loop Statements 63 (10)
Exit Statements 64 (2)
Next Statements 66 (1)
While Loops 67 (2)
For Loops 69 (3)
Summary of Loop Statements 72 (1)
Assertion and Report Statements 73 (8)
Exercises 78 (3)
Composite Data Types and Operations 81 (22)
Arrays 82 (8)
Multidimensional Arrays 84 (1)
Array Aggregates 85 (3)
Array Attributes 88 (2)
Unconstrained Array Types 90 (4)
Strings 91 (1)
Bit Vectors 91 (1)
Standard-Logic Arrays 91 (1)
String and Bit-String Literals 92 (1)
Unconstrained Array Ports 92 (2)
Array Operations and Referencing 94 (3)
Array Slices 95 (1)
Array Type Conversions 96 (1)
Records 97 (6)
Record Aggregates 100 (1)
Exercises 101 (2)
Basic Modeling Constructs 103 (58)
Entity Declarations 104 (2)
Architecture Bodies 106 (2)
Concurrent Statements 107 (1)
Signal Declarations 107 (1)
Behavioral Descriptions 108 (28)
Signal Assignment 109 (2)
Signal Attributes 111 (2)
Wait Statements 113 (4)
Delta Delays 117 (3)
Transport and Inertial Delay Mechanisms 120 (6)
Process Statements 126 (1)
Concurrent Signal Assignment Statements 127 (6)
Concurrent Assertion Statements 133 (1)
Entities and Passive Processes 134 (2)
Structural Descriptions 136 (8)
Component Instantiation and Port Maps 136 (8)
Design Processing 144 (17)
Analysis 144 (2)
Design Libraries, Library Clauses and Use 146 (2)
Clauses
Elaboration 148 (3)
Execution 151 (1)
Exercises 152 (9)
Case Study: A Pipelined Multiplier Accumulator 161 (28)
Algorithm Outline 162 (3)
MAC Entity Declaration 164 (1)
A Behavioral Model 165 (7)
Testing the Behavioral Model 169 (3)
A Register-Transfer-Level Model 172 (17)
Modules in the Register-Transfer-Level 173 (8)
Model
The Register-Transfer-Level Architecture 181 (4)
Body
Testing the Register-Transfer-Level Model 185 (2)
Exercises 187 (2)
Subprograms 189 (36)
Procedures 190 (6)
Return Statement in a Procedure 195 (1)
Procedure Parameters 196 (11)
Signal Parameters 200 (3)
Default Values 203 (1)
Unconstrained Array Parameters 204 (1)
Summary of Procedure Parameters 205 (2)
Concurrent Procedure Call Statements 207 (2)
Functions 209 (5)
Functional Modeling 211 (1)
Pure and Impure Functions 212 (1)
The Function Now 213 (1)
Overloading 214 (3)
Overloading Operator Symbols 215 (2)
Visibility of Declarations 217 (8)
Exercises 221 (4)
Packages and Use Clauses 225 (16)
Package Declarations 226 (7)
Subprograms in Package Declarations 230 (1)
Constants in Package Declarations 231 (2)
Package Bodies 233 (2)
Use Clauses 235 (2)
The Predefined Package Standard 237 (4)
Exercises 239 (2)
Aliases 241 (10)
Aliases for Data Objects 242 (3)
Aliases for Non-Data Items 245 (6)
Exercises 248 (3)
Case Study: A Bit-Vector Arithmetic Package 251 (18)
The Package Interface 252 (3)
The Package Body 255 (9)
An ALU Using the Arithmetic Package 264 (5)
Exercises 266 (3)
Resolved Signals 269 (22)
Basic Resolved Signals 270 (8)
Composite Resolved Subtypes 274 (4)
Summary of Resolved Subtypes 278 (1)
IEEE Std_Logic_1164 Resolved Subtypes 278 (3)
Resolved Signals and Ports 281 (3)
Resolved Ports 282 (2)
Driving Value Attribute 284 (1)
Resolved Signal Parameters 284 (7)
Exercises 286 (5)
Generic Constants 291 (8)
Parameterizing Behavior 292 (3)
Parameterizing Structure 295 (4)
Exercises 297 (2)
Components and Configurations 299 (32)
Components 300 (4)
Component Declarations 300 (1)
Component Instantiation 301 (2)
Packaging Components 303 (1)
Configuring Component Instances 304 (15)
Basic Configuration Declarations 305 (2)
Configuring Multiple Levels of Hierarchy 307 (3)
Direct Instantiation of Configured 310 (1)
Entities
Generic and Port Maps in Configurations 311 (6)
Deferred Component Binding 317 (2)
Configuration Specifications 319 (12)
Incremental Binding 320 (6)
Exercises 326 (5)
Generate Statements 331 (24)
Generating Iterative Structures 332 (5)
Conditionally Generating Structures 337 (6)
Recursive Structures 340 (3)
Configuration of Generate Statements 343 (12)
Exercises 349 (6)
Case Study: The DLX Computer System 355 (88)
Overview of the DLX CPU 356 (9)
DLX Registers 356 (1)
DLX Instruction Set 357 (4)
DLX External Interface 361 (4)
A Behavioral Model 365 (25)
The DLX Types Package 365 (1)
The DLX Entity Declaration 366 (1)
The DLX Instruction Set Package 366 (8)
The DLX Behavioral Architecture Body 374 (16)
Testing the Behavioral Model 390 (8)
The Test-Bench Clock Generator 390 (1)
The Test-Bench Memory 391 (5)
The Test-Bench Architecture Body and 396 (2)
Configuration
A Register-Transfer-Level Model 398 (39)
The Arithmetic and Logic Unit 399 (4)
The Registers 403 (3)
The Register File 406 (3)
The Multiplexer 409 (1)
The Extenders 409 (2)
The Architecture Body 411 (5)
The Controller 416 (18)
The Configuration Declaration 434 (3)
Testing the Register-Transfer-Level Model 437 (6)
Exercises 441 (2)
Guards and Blocks 443 (26)
Guarded Signals and Disconnection 444 (8)
The Driving Attribute 448 (1)
Guarded Ports 448 (2)
Guarded Signal Parameters 450 (2)
Blocks and Guarded Signal Assignment 452 (7)
Explicit Guard Signals 456 (1)
Disconnection Specifications 457 (2)
Using Blocks for Structural Modularity 459 (10)
Generics and Ports in Blocks 461 (2)
Configuring Designs with Blocks 463 (2)
Exercises 465 (4)
Access Types and Abstract Data Types 469 (28)
Access Types 470 (5)
Access Type Declarations and Allocators 470 (2)
Assignment and Equality of Access Values 472 (2)
Access Types for Records and Arrays 474 (1)
Linked Data Structures 475 (6)
Deallocation and Storage Management 479 (2)
Abstract Data Types Using Packages 481 (16)
Container ADTs 485 (8)
Exercises 493 (4)
Files and Input/Output 497 (30)
Files 498 (13)
File Declarations 498 (1)
Reading from Files 499 (3)
Writing to Files 502 (3)
Files Declared in Subprograms 505 (1)
Explicit Open and Close Operations 506 (3)
File Parameters in Subprograms 509 (2)
Portability of Files 511 (1)
The Package Textio 511 (16)
Textio Read Operations 513 (7)
Textio Write Operations 520 (2)
Reading and Writing User-Defined Types 522 (1)
Exercises 523 (4)
Case Study: Queuing Networks 527 (36)
Queuing Network Concepts 528 (1)
Queuing Network Modules 529 (27)
Random Number Generator 529 (4)
A Package for Token and Arc Types 533 (2)
The Token Source Module 535 (4)
The Token Sink Module 539 (2)
The Queue Module 541 (6)
The Token Server Module 547 (2)
The Fork Module 549 (4)
The Join Module 553 (3)
A Queuing Network for a Disk System 556 (7)
Exercises 562 (1)
Attributes and Groups 563 (28)
Predefined Attributes 564 (9)
Attributes of Scalar Types 564 (1)
Attributes of Array Types and Objects 565 (1)
Attributes of Signals 565 (1)
Attributes of Named Items 566 (7)
User-Defined Attributes 573 (12)
Attribute Declarations 573 (1)
Attribute Specifications 574 (10)
The Attribute Foreign 584 (1)
Groups