Preface	p. xv
Acknowledgements	p. xxi
RF Design and ESD	p. 1
Fundamental Concepts of ESD Design	p. 1
Fundamental Concepts of RF ESD Design	p. 4
Key RF ESD Contributions	p. 10
Key RF ESD Patents	p. 13
ESD Failure Mechanisms	p. 13
RF CMOS ESD Failure Mechanisms	p. 14
Silicon Germanium ESD Failure Mechanisms	p. 15
Silicon Germanium Carbon ESD Failure Mechanisms in Silicon Germanium Carbon Devices	p. 15
Gallium Arsenide Technology ESD Failure Mechanisms	p. 16
Indium Gallium Arsenide ESD Failure Mechanisms	p. 16
RF Bipolar Circuits ESD Failure Mechanisms	p. 17
RF Basics	p. 17
Two-Port Network Parameters	p. 21
Z-Parameters	p. 21
Y-Parameters	p. 22
S-Parameters	p. 22
T-Parameters	p. 23
Stability: RF Design Stability and ESD	p. 24
Device Degradation and ESD Failure	p. 26
ESD-Induced D.C. Parameter Shift and Failure Criteria	p. 26
RF Parameters, ESD Degradation, and Failure Criteria	p. 28
RF ESD Testing	p. 29
ESD Testing Models	p. 29
RF Maximum Power-to-Failure and ESD Pulse Testing Methodology	p. 33
ESD-Induced RF Degradation and S-Parameter Evaluation Test Methodology	p. 37
Time Domain Reflectometry (TDR) and Impedance Methodology for ESD Testing	p. 39
Time Domain Reflectometry (TDR) ESD Test System Evaluation	p. 40
ESD Degradation System Level Method - Eye Tests	p. 44
Product Level ESD Test and RE Functional Parameter Failure	p. 46
Combined RF and ESD TLP Test Systems	p. 48
Closing Comments and Summary	p. 51
Problems	p. 52
References	p. 53
RF ESD Design	p. 61
ESD Design Methods: Ideal ESD Networks and RF ESD Design Windows	p. 61
Ideal ESD Networks and the Current-Voltage d.c. Design Window	p. 61
Ideal ESD Networks in the Frequency Domain Design Window	p. 63
RF ESD Design Methods: Linearity	p. 64
RF ESD Design: Passive Element Quality Factors and Figures of Merit	p. 68
RF ESD Design Methods: Method of Substitution	p. 70
Method of Substitution of Passive Element to ESD Network Element	p. 71
Substitution of ESD Network Element to Passive Element	p. 72
RF ESD Design Methods: Matching Networks and RF ESD Networks	p. 73
RF ESD Method - Conversion of Matching Networks to ESD Networks	p. 74
RF ESD Method: Conversion of ESD Networks into Matching Networks	p. 76
Conversion of ESD Networks into L-Match Networks	p. 76
Conversion of ESD Networks into [Pi]-Match Networks	p. 77
Conversion of ESD Networks into T-Match Networks	p. 78
RF ESD Design Methods: Inductive Shunt	p. 79
RF ESD Design Methods: Cancellation Method	p. 82
Quality Factors and the Cancellation Method	p. 82
Inductive Cancellation of Capacitance Load and Figures of Merit	p. 83
Cancellation Method and ESD Circuitry	p. 85
RF ESD Design Methods: Impedance Isolation Technique Using LC Resonator	p. 89
RF ESD Design Methods: Lumped versus Distributed Loads	p. 91
RF ESD Distributed Load with Coplanar Wave Guides	p. 92
RF ESD Distribution Coplanar Waveguides Analysis Using ABCD Matrices	p. 93
ESD RF Design Synthesis and Floor Planning: RF, Analog, and Digital Integration	p. 95
ESD Power Clamp Placement Within a Domain	p. 96
Power Bus Architecture and ESD Design Synthesis	p. 97
V[subscript DD]-to-V[subscript SS] Power Rail Protection	p. 98
VoD-to-Analog Vdd and Vdo-Io-RF Vcc Power Rail Protection	p. 99
Interdomain BSD Protection Networks	p. 100
ESD Circuits and RF Bond Pad Integration	p. 101
ESD Structures Under Wire Bond Pads	p. 103
Summary and Closing Comments	p. 106
Problems	p. 106
References	p. 108
RF CMOS and ESD	p. 111
RF CMOS: ESD Device Comparisons	p. 111
Circular RF ESD Devices	p. 116
RF ESD Design-ESD Wiring Design	p. 118
RF Passives: ESD and Schottky Barrier Diodes	p. 120
RF Passives: ESD and Inductors	p. 122
RF Passives: ESD and Capacitors	p. 127
Metal-oxide-Semiconductor and Metal-Insulator-Metal Capacitors	p. 128
Varactors and Hyper-Abrupt Junction Varactor Capacitors	p. 128
Metal-ILD-Metal Capacitors	p. 129
Vertical Parallel Plate (VPP) Capacitors	p. 130
Summary and Closing Comments	p. 131
Problems	p. 132
References	p. 133
RF CMOS ESD Networks	p. 139
RF CMOS Input Circuits	p. 139
RF CMOS ESD Diode Networks	p. 139
RF CMOS Diode String ESD Network	p. 143
RF CMOS: Diode-Inductor ESD Networks	p. 145
RF Inductor-Diode ESD Networks	p. 147
RF Diode-Inductor ESD Networks	p. 148
RF CMOS Impedance Isolation LC Resonator ESD Networks	p. 149
RF CMOS LC-Diode ESD Networks	p. 150
RF CMOS Diode-LC ESD Networks	p. 150
Experimental Results of the RF CMOS LC-Diode Networks	p. 151
RF CMOS LNA ESD Design	p. 152
RF LNA ESD Design: Low Resistance ESD Inductor and ESD Diode Clamping Elements in [Pi]-Configuration	p. 153
RF CMOS T-Coil Inductor ESD Input Network	p. 157
RF CMOS Distributed ESD Networks	p. 159
RF CMOS Distributed RF ESD Networks	p. 159
RF CMOS Distributed RF ESD Networks using Series Inductor and Dual-Diode Shunt	p. 160
RF CMOS Distributed RF ESD Networks using Series Inductor and MOSFET Parallel Shunt	p. 163
RF CMOS Distributed ESD Networks: Transmission Lines and Coplanar Waveguides	p. 165
RF CMOS: ESD and RF LDMOS Power Technology	p. 167
RF CMOS ESD Power Clamps	p. 170
RC-Triggered MOSFET ESD Power Clamp	p. 172
High Voltage RC-Triggered MOSFET ESD Power Clamp	p. 174
Voltage-Triggered MOSFET ESD Power Clamps	p. 175
Summary and Closing Comments	p. 176
Problems	p. 177
References	p. 178
Bipolar Physics	p. 183
Bipolar Device Physics	p. 183
Bipolar Transistor Current Equations	p. 183
Bipolar Current Gain and Collector-to-Emitter Transport	p. 184
Unity Current Gain Cutoff Frequency	p. 185
Unity Power Gain Cutoff Frequency	p. 186
Transistor Breakdown	p. 186
Avalanche Multiplication and Breakdown	p. 186
Bipolar Transistor Breakdown	p. 188
Kirk Effect	p. 190
Johnson Limit: Physical Limitations of the Transistor	p. 191
Voltage-Frequency Relationship	p. 191
Johnson Limit Current-Frequency Formulation	p. 193
Johnson Limit Power Formulation	p. 194
RF Instability: Emitter Collapse	p. 195
ESD RF Design Layout: Emitter, Base, and Collector Configurations	p. 201
ESD RF Design Layout: Utilization of a Second Emitter (Phantom Emitter)	p. 204
ESD RF Design Layout: Emitter Ballasting	p. 208
ESD RF Design Layout: Thermal Shunts and Thermal Lenses	p. 210
Base-Ballasting and RF Stability	p. 211
Summary and Closing Comments	p. 213
Problems	p. 213
References	p. 214
Silicon Germanium and ESD	p. 217
Heterojunctions and Silicon Germanium Technology	p. 217
Silicon Germanium HBT Devices	p. 218
Silicon Germanium Device Structure	p. 219
Silicon Germanium Physics	p. 221
Silicon Germanium Carbon	p. 224
Silicon Germanium ESD Measurements	p. 226
Silicon Germanium Collector-to-Emitter ESD Stress	p. 227
ESD Comparison of Silicon Germanium HBT and Silicon BJT	p. 229
SiGe HBT Electrothermal Human Body Model (HBM) Simulation of Collector-Emitter Stress	p. 232
Silicon Germanium Carbon Collector-Emitter ESD Measurements	p. 233
Silicon Germanium Transistor Emitter-Base Design	p. 237
Epitaxial-Base Heterojunction Bipolar Transistor (HBT) Emitter-Base Design	p. 238
Emitter-Base Design RF Frequency Performance Metrics	p. 240
SiGe HBT Emitter-Base Resistance Model	p. 240
SiGe HBT Emitter-Base Design and Silicide Placement	p. 241
Self-Aligned (SA) Emitter-Base Design	p. 245
Non-self aligned (NSA) Emitter-Base Design	p. 248
NSA Human Body Model (HBM) Step Stress	p. 249
Transmission Line Pulse (TLP) Step Stress	p. 250
RF Testing of SiGe HBT Emitter-Base Configuration	p. 251
Unity Current Gain Cutoff Frequency-Collector Current Plots	p. 254
Silicon Germanium Carbon - ESD-Induced S-Parameter Degradation	p. 256
Electrothermal Simulation of Emitter-Base Stress	p. 258
Field-Oxide (FOX) Isolation Defined Silicon Germanium Heterojunction Bipolar Transistor HBM Data	p. 259
Silicon Germanium HBT Multiple-Emitter Study	p. 260
Summary and Closing Comments	p. 262
Problems	p. 262
References	p. 263
Gallium Arsenide and ESD	p. 269
Gallium Arsenide Technology and ESD	p. 269
Gallium Arsenide Energy-to-Failure and Power-to-Failure	p. 269
Gallium Arsenide ESD Failures in Active and Passive Elements	p. 272
Gallium Arsenide HBT Devices and ESD	p. 273
Gallium Arsenide HBT Device ESD Results	p. 274
Gallium Arsenide HBT Diode Strings	p. 275
Gallium Arsenide HBT-Based Passive Elements	p. 277
GaAs HBT Base-Collector Varactor	p. 277
Gallium Arsenide Technology Table of Failure Mechanisms	p. 279
Indium Gallium Arsenide and ESD	p. 279
Indium Phosphide (InP) and ESD	p. 281
Summary and Closing Comments	p. 281
Problems	p. 281
References	p. 282
Bipolar Receiver Circuits and Bipolar ESD Networks	p. 287
Bipolar Receivers and ESD	p. 287
Single Ended Common-Emitter Receiver Circuits	p. 288
Single-Ended Bipolar Receiver with D.C. Blocking Capacitors	p. 289
Single-Ended Bipolar Receiver with D.C. Blocking Capacitors and ESD Protection	p. 290
Bipolar Single-Ended Common-Emitter Receiver Circuit with Feedback Circuit	p. 291
Bipolar Single-Ended Common-Emitter Circuit with Resistor Feedback Element	p. 291
Bipolar Single-Ended Common-Emitter Receiver Circuit with Resistor-Capacitor Feedback Element	p. 292
Bipolar Single-Ended Common-Emitter Receiver Circuit with Emitter Degeneration	p. 293
Bipolar Single-Ended Common Emitter Circuit with Balun Output	p. 297
Bipolar Single-Ended Series Cascode Receiver Circuits	p. 298
Bipolar Differential Receiver Circuits	p. 300
Bipolar Differential Cascode Common-Emitter Receiver Circuits	p. 302
Bipolar ESD Input Circuits	p. 303
Diode-Configured Bipolar ESD Input Circuits	p. 307
Bipolar ESD Input: Resistor Grounded Base Bipolar ESD Input	p. 308
Bipolar-Based ESD Power Clamps	p. 312
Bipolar Voltage-Triggered ESD Power Clamps	p. 312
Zener Breakdown Voltage-Triggered ESD Power Clamps	p. 312
BV[subscript CEO] Voltage-Triggered ESD Power Clamps	p. 318
Mixed Voltage Interface Forward-Bias Voltage and BV[subscript CEO] Breakdown Synthesized Bipolar ESD Power Clamps	p. 323
Ultra-Low Voltage Forward-Biased Voltage-Trigger BiCMOS ESD Power Clamps	p. 328
Capacitively Triggered BiCMOS ESD Power Clamps	p. 332
Bipolar ESD Diode String and Triple-Well Power Clamps	p. 334
Summary and Closing Comments	p. 335
Problems	p. 335
References	p. 337
RF and ESD Computer-Aided Design (CAD)	p. 339
RF ESD Design Environment	p. 339
Electrostatic Discharge and Radio Frequency (RF) Cosynthesis Design Methods	p. 339
ESD Hierarchical Pcell Physical Layout Generation	p. 340
ESD Hierarchical Pcell Schematic Generation	p. 341
ESD Design with Hierarchical Parameterized Cells	p. 341
Hierarchical Pcell Graphical Method	p. 342
Hierarchical Pcell Schematic Method	p. 344
ESD Design of RF CMOS-Based Hierarchical Parameterized Cells	p. 347
RF BiCMOS ESD Hierarchical Parameterized Cell	p. 349
BiCMOS ESD Input Networks	p. 350
BiCMOS ESD Rail-to-Rail	p. 353
BiCMOS ESD Power Clamps	p. 354
Advantages and Limitations of the RF ESD Design System	p. 359
Guard Ring P-Cell Methodology	p. 362
Guard Rings for Internal and External Latchup Phenomena	p. 362
Guard Ring Theory	p. 363
Guard Ring Design	p. 365
Guard Ring Characterization	p. 367
Summary and Closing Comments	p. 370
Problems	p. 370
References	p. 371
Alternative ESD Concepts: On-Chip and Off-Chip ESD Protection Solutions	p. 375
Spark Gaps	p. 375
Field Emission Devices	p. 378
Field Emission Device (FED) as ESD Protection	p. 378
Field Emission Device in Gallium Arsenide Technology	p. 379
Field Emission Device Electronic Blunting Effect	p. 380
Field Emission Device Multiemitter ESD Design	p. 380
Field Emission Device (FED) ESD Design Practices	p. 382
Off-Chip Protection and Off-Chip Transient Suppression Devices	p. 382
Off-Chip Transient Voltage Suppression (TVS) Devices	p. 383
Off-Chip Polymer Voltage Suppression (PVS) Devices	p. 384
Package-Level Mechanical ESD Solutions	p. 386
RE Proximity Communications Chip-to-Chip ESD Design Practices	p. 387
Summary and Closing Comments	p. 388
Problems	p. 389
References	p. 389
Index	p. 391
Table of Contents provided by Ingram. All Rights Reserved.

책소개

Electrostatic Discharge (ESD) within RF devices can result in the malfunctioning of nearby electronic equipment. This volume is designed as the third in a series of three books addressing Electrostatic Discharge (ESD) physics, devices, circuits and design. It will be the first book to address the increasingly important area of ESD within RF devices and circuits.

저자소개

Voldman, Stephen Howard [저] 신작알림 SMS신청

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